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EVALUATION KIT AVAILABLE
1
TC530 TC534
5V PRECISION DATA ACQUISITION SUBSYSTEMS
FEATURES
s s s s s s s s s s Precision (up to 17 Bits) A/D Converter 3 Wire Serial Port Flexible: User Can Trade-Off Conversion Speed Against Resolution Single Supply Operation -5V Output Pin 4 Input, Differential Analog MUX (TC534) Automatic Input Polarity and Overrange Detection Low Operating Current ............................ 5mA Max Wide Analog Input Range ...................... 4.2V Max Cost Effective
GENERAL DESCRIPTION
The TC530/534 are serial analog data acquisition subsystems ideal for high precision measurements (up to 17 bits plus sign). The TC530 consists of a dual slope integrating A/D converter, negative power supply generator and 3 wire serial interface port. The TC534 is identical to the TC530, but adds a four channel differential input multiplexer. Key A/D converter operating parameters (Auto Zero and Integration time) are programmable, allowing the user to trade-off conversion time for resolution. Data conversion is initiated when the RESET input is brought low. After conversion, data is loaded into the output shift register and EOC is asserted indicating new data is available. The converted data (plus Overrange and polarity bits) is held in the output shift register until read by the processor, or until the next conversion is completed allowing the user to access data at any time. The TC530/534 timebase can be derived from an external crystal of 2MHz (max), or from an external frequency source. The TC530/534 requires a single 5V power supply and features a - 5V, 10mA output which can be used to supply negative bias to other components in the system.
2 3 4 5 6
Optional Power-On Reset Cap
ORDERING INFORMATION
Part No.
TC530COI TC530CPJ TC534CKW TC534CPL TC530EV
Package
Temp. Range
28-Pin SOIC 0C to +70C 28-Pin Plastic DIP (300 Mil.) 0C to +70C 44-Pin PQFP 0C to +70C 40-Pin Plastic DIP 0C to +70C Evaluation Kit for TC530/534
FUNCTIONAL BLOCK DIAGRAM
+5V + V (TC530 Only) IN V-
IN
CINT RINT CAZ
CREF
VDD
10k
100k
TC05
.01F
VDD
BUF CAZ
INT
+ - CREF CREF Dual Slope A/D Converter CMPTR A B
+ VREF
- VREF
VDD
ACOM
CH1 + CH1 - CH2 + CH2 - CH3 + CH3 - CH4 + CH4 - DIF. MUX (TC534 Only)
IN + IN -
0.01F RESET EOC
TC534 (Only)
TC530 TC534
VDD State Machine
DC-TO-DC CONVERTER
R/W Serial Port DIN DOUT DCLK
7
Oscillator (/ 4)
A0 A1
OSC
VSS CAP+ CAP -
OSCIN
OSCOUT
Negative Supply Output
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TC530/534-3 11/14/96
TELCOM SEMICONDUCTOR, INC.
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ........................................................... +6V + - Analog Input Voltage (VIN or VIN) ....................... VDD to VSS Logic Input Voltage ................. (VDD + 0.3V) to (GND - 0.3V) Ambient Operating Temperature Range Plastic DIP Package .............................................. (C) 0C to +70C SOIC Package (C) .............................. 0C to +70C PQFP Package (C) .............................. 0C to +70C Storage Temperature Range .................... - 65C to +150C Lead Temperature (Soldering, 10 sec) ..................... +300C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = +25C Symbol
VDD VCCD PD IS ICCD
TA = 0C to +70C Max
5.5 5.5 25 2.5 1.5
Parameter
Analog Power Supply Voltage Digital Power Supply Voltage TC530/534 Total Power Dissipation Supply Current (VS + PIN) Supply Current (VCCD PIN)
Test Conditions
Min
4.5 4.5 -- -- --
Typ
5.0 5.0 -- 1.8 --
Min
4.5 4.5 -- -- --
Typ
-- -- -- -- --
Max
5.5 5.5 -- 3.0 1.7
Unit
V V mW mA mA
VDD = VCCD = 5V
fOSC = 1MHz
ELECTRICAL CHARACTERISTICS: VDD = VCCD, CAZ = CREF = 0.47F, unless otherwise specified.
TA = +25C Symbol Analog
R ZSE ENL NL ZSTC SYE FSTC IIN VCMR VINT VIN VREF tD Resolution Zero-Scale Error with Auto Zero Phase End Point Linearity Max Deviation from Best Straight Line Fit Zero-Scale Temperature Coefficient Roll-Over Error Full-Scale Temperature Coefficient Input Current Common-Mode Voltage Range Integrator Output Swing Analog Input Signal Range Voltage Reference Range Zero Crossing Comparator Note 1 -- -- -- -- -- Note 3 Ext. VREF TC = 0ppm/C VIN = 0V -- -- -- VSS + 1.5 VSS + 0.9 VSS + 1.5 VSS + 1 -- -- -- 0.015 0.008 -- .012 -- 6 -- -- -- -- 2.0 17 0.5 0.030 0.015 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.005 0.015 -- 1 .03 10 -- 17 0.012 Bits % F.S.
TA = 0C to +70C Max Min Typ Max Unit
Parameter
Test Conditions
Min
Typ
Note 1 and 2 Notes 1 and 2
0.045 % F.S. -- % F.S. 2 -- -- -- V/C % F.S. ppm/C pA V V V V sec
VDD - 1.5 VSS + 1.5 -- VDD - 0.9 VSS + 0.9 -- VDD - 1.5 VSS + 1.5 -- VDD - 1 VDD + 1 --
-- -- 3.0
VDD - 1.5 VDD - 0.9 VDD - 1.5 VDD - 1
--
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TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
ELECTRICAL CHARACTERISTICS: Serial Port Interface: VCCD = +5V, unless otherwise specified.
TA = +25C Symbol
VIH VIL IIN VOL
1
TA = 0C to +70C Max
-- 0.8 10 0.3
2
Unit
V V A V
Parameter
Input Logic HIGH Level Input Logic LOW Level Input Current (DI, DO, DCLK) Logic LOW Output Voltage (EOC)
Test Conditions
Min
2.5 -- -- --
Typ
-- -- -- 0.2
Min
2.5 -- -- --
Typ
-- -- -- --
Max
-- 0.8 -- 0.35
IOUT = 250A
3 4 5 6 7
ELECTRICAL CHARACTERISTICS: Serial Port Interface: VCCD = +5V, unless otherwise specified.
TA = +25C Symbol
tR, tF FXTL FEXT tRS tRD tDRS tPWL tPWH tDR
TA = 0C to +70C Max
250 2.0 4.0 -- -- -- -- -- --
Parameter
Rise and Fall Times (EOC, DI, DO) Crystal Frequency External Frequency on OSCIN Read Setup Time Read Delay Time DCLK to DOUT Delay DCLK LOW Pulse Width DCLK HIGH Pulse Width Data Ready Delay
Test Conditions
CL = 10pF
Min
-- -- -- 1 250 450 150 150 200
Typ
-- -- -- -- -- -- -- -- --
Min
-- -- -- -- -- -- -- -- --
Typ
250 -- -- 1 250 450 150 150 200
Max
-- 2.0 4.0 -- -- -- -- -- --
Unit
nsec MHz MHz sec nsec nsec nsec nsec nsec
ELECTRICAL CHARACTERISTICS: DC/DC Converter Section: VDD = +5V, unless otherwise specified.
TA = +25C Symbol
ROUT fCLK IOUT
TA = 0C To +70C Max
85 -- 10
Parameter
Output Resistance Oscillator Frequency VSS Output Current
Test Conditions
IOUT = 10mA COSC = 0
Min
-- -- --
Typ
65 100 --
Min
-- -- --
Typ
-- -- --
Max
100 -- 10
Unit
kHz mA
ELECTRICAL CHARACTERISTICS: Multiplexer: VDD = +5V (Note 4), unless otherwise specified.
TA = +25C Symbol
VINMAX RDSON
Notes: 1. 2. 3. 4.
TA = 0C to +70C Max
2.5 10
Parameter
Maximum Input Voltage Drain/Source ON Resistance
Test Conditions
Min
- 2.5 --
Typ
-- 6
Min
-2.5 --
Typ
-- --
Max
2.5 --
Unit
V k
Integrate time 66msec, Auto Zero time 66msec, VINT (pk) = 4V. End point linearity at , , F.S. after full scale adjustment. Roll-over error is related to capacitor used for CINT (See "Recommended Suppliers for CINT", Table 2). TC534 Only.
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
PIN CONFIGURATIONS
VSS CINT CAZ BUF ACOM - CREF
+ CREF - V REF + V REF - VIN + VIN
1 2 3 4 5 6 7 8 9 10 11
28 CAP - 27 AGND 26 CAP + 25 VDD 24 NC 23 OSC 22 VCCD 21 RESET 20 EOC 19 R/W 18 DIN 17 DCLK 16 DOUT 15 OSCIN
VSS CINT CAZ BUF ACOM - CREF CREF
- V REF + +
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CAP - AGND CAP + VDD N/C OSC VCCD RESET EOC R/W DIN DCLK DOUT OSCIN
TC530CPJ
TC530COI
22 21 20 19 18 17 16 15
V REF
- VIN + VIN
DGND 12 N/C 13 OSCOUT 14
DGND N/C OSCOUT
AGND
CAP +
CAP -
CINT
BUF
CAZ
VSS
N/C
VDD
35
VSS CINT CAZ BUF ACOM - CREF CREF
- V REF + +
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 CAP - 39 AGND 38 CAP+ 37 VDD 36 N/C 35 N/C 34 OSC 33 N/C 32 31 VCCD N/C RESET N/C ACOM - CREF CREF
- V REF + V REF + 44 43 42 41 40 39 38 37 36 34
N/C
N/C
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 14 17 18 19 20 21 22
33 32 31 30 29 28
N/C OSC N/C VCCD N/C RESET N/C N/C N/C EOC R/W
V REF CH4- CH3- CH2- CH1- CH4+ CH3+ CH2+ CH1+ DGND A1 A0
TC534CKW
CH4- CH3- CH2- CH1- CH4+
27 26 25 24 23
TC534CPL
30
29 N/C 28 N/C
27 EOC 26 25 24 23 22 R/W DIN DCLK DOUT OSCIN
CH1+
OSCOUT
CH3+ CH2+
DOUT
DCLK
21 OSCOUT
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TELCOM SEMICONDUCTOR, INC.
OSCIN
DGND
DIN
A1
A0
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
PIN DESCRIPTION
Pin No. (TC530 28-Pin PDIP, 300 Mil.)
1
1
Pin No. (TC530 28-Pin SOIC)
1
Pin No (TC534 40-Pin PDIP)
1
Pin No. (TC534 44-Pin PQFP)
40
2
Symbol
VSS
Description
Analog Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to provide negative bias to other devices in the system. Analog Output. Integrator capacitor connection and integrator output. Analog Input. Auto Zero capacitor connection. Analog Output. Integrator capacitor connection and voltage buffer output. Analog Input. This pin is ground for all of the analog switches in the A/D converter. It is grounded for most applications. - ACOM and the input common pin (VIN or Chx-) should be within the common mode range, CMR. Analog Input. Reference cap negative connection. Analog Input. Reference cap positive connection. Analog Input. External voltage reference negative connection. Analog Input. External voltage reference positive connection. Analog Input. Multiplexer channel 4 negative differential analog input. Analog Input. Multiplexer channel 3 negative differential analog input. Analog Input. Multiplexer channel 2 negative differential analog input. Analog Input. Multiplexer channel 1 negative differential analog input. Analog Input. Multiplexer channel 4 positive differential analog input. Analog Input. Multiplexer channel 3 positive differential analog input. Analog Input. Multiplexer channel 2 positive differential analog input. Analog Input. Multiplexer channel 1 positive differential analog input. Analog Input. Negative differential analog voltage input. Analog Input. Positive differential analog voltage input. Analog Input. Ground connection for serial port circuit. Logic Level Input. Multiplexer address MSB. Logic Level Input. Multiplexer address LSB. Analog Input. Timebase for state machine. This pin connects to one side of an AT-cut crystal having an effective series resistance of 100 (typ) and a parallel capacitance of 20pF If an external frequency source is used to clock the TC530/534, this pin must be left floating.
2 3 4 5
2 3 4 5
2 3 4 5
41 42 43 2
CINT CAZ BUF ACOM
3 4 5 6 7
6 7 8 9 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 10 11 12 Not Used Not Used 14
6 7 8 9 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 10 11 12 Not Used Not Used 14
6 7 8 9 10 11 12 13 14 15 16 17 Not Used Not Used 18 19 20 21
3 4 5 6 7 8 9 10 11 12 13 14 Not Used Not Used 15 16 17 18
- CREF + CREF - VREF + VREF CH4-
CH3- CH2- CH1- CH4+ CH3+ CH2+ CH1+
- VIN + VIN DGND A1 A0 OSCOUT
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
PIN DESCRIPTION (Cont.)
Pin No. Pin No. (TC530 (TC530 28-Pin 28-Pin PDIP, 300 Mil.) SOIC)
15 15
Pin No (TC534 40-Pin PDIP)
22
Pin No. (TC534 44-Pin PQFP)
19
Symbol
OSCIN
Description
Analog Input. This pin connects to the other side of the crystal described in OSCOUT above. The TC530/534 may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (Max). If an external frequency source is used, OSCOUT must be left floating. A maximum operating frequency of 2MHz (crystal) or 4MHz (external clock source) is permitted. Logic Level Output. Serial port data output pin. This pin is enabled only when R/W is high. Logic Input, Positive and Negative Edge Triggered. Serial port clock. When R/W is high, serial data is clocked out of the TC530/534A (on DOUT) at each HIGH-to-LOW transition of DCLK. A/D initialization data (LOAD VALUE) is clocked into the TC530/534 (on DIN) at each LOW-to-HIGH transition of DCLK. A maximum serial port DCLK frequency of 3MHz is permitted. Logic Level Input. Serial port input pin. The A/D converter integration time (TINT) and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. Logic Level Input. This pin must be brought low to perform a write to the serial port (e.g. initialize the A/D converter). The DOUT pin of the serial port is enabled only when this pin is high. Open Drain Output. End-of-Conversion (EOC) is asserted any time the TC530/534 is in the AZ phase of conversion. This occurs when either the TC530/534 initiates a normal AZ phase, or when RESET is pulled high. EOC is returned high when the TC530/534 exits AZ. Since EOC is driven low immediately following completion of a conversion cycle, it can be used as a DATA READY processor interrupt. Logic Level Input. It is necessary to force the TC530/534 into the Auto Zero phase when power is initially applied. This is accomplished by momentarily taking RESET high. Using an I/O port line from the microprocessor, or by applying an external system reset signal, or by connecting a 0.01F capacitor from the RESET input to VSS. Conversions are performed continuously as long as RESET is low and conversion is halted when RESET is high. RESET may therefore be used in a complex system to momentarily suspend conversion (for example while the address lines of an input multiplexer are changing state). In this case, RESET should be pulled high only when the EOC is LOW to avoid excessively long integrator discharge times which could result in erroneous conversion (see Applications Section).
16 17
16 17
23 24
20 21
DOUT DCLK
18
18
25
22
DIN
19
19
26
23
R/W
20
20
27
24
EOC
21
21
30
28
RESET
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
PIN DESCRIPTION (Cont.)
Pin No. (TC530 28-Pin PDIP, 300 Mil.)
22
1
Pin No. (TC530 28-Pin SOIC)
22
Pin No (TC534 40-Pin PDIP)
32
Pin No. (TC534 44-Pin PQFP)
30
2
Symbol
VCCD
Description
Analog Input. Power supply connection for digital logic and serial port. Proper power-up sequencing is critical, see the Applications section. Input. The negative power supply converter normally runs at a frequency of 100kHz. This frequency can be slowed down to reduce quiescent current by connecting an external capacitor + between this pin and VS. (See Typical Characteristics). Analog Input. Power supply connection for the A/D analog section and DC-DC converter. Proper power-up sequencing is critical, see the Applications section. Analog Input. Storage capacitor positive connection for the DC/DC converter. Analog Input. Ground connection for DC/DC converter. Analog Input. Storage capacitor negative connection for the DC/DC converter. No connect. Do not connect any signal to these pins.
23
23
34
32
OSC
3 4 5
25
25
37
35
VDD
26 27 28 13, 24
26 27 28 13, 24
38 39 40
36 37 38
CAP+ AGND CAP- NC
28, 29, 31, 1, 25, 26, 27 33, 35, 36 29, 31, 33, 34, 39, 44,
READ TIMING
WRITE TIMING
tRS
WRITE DEFAULT TIMING
R/W tRD EOC
R/W tLS DIN
R/W tLDL DIN tDLS tPWL tLDS
DOUT tDRS DCLK tPWL DCLK
READ FORMAT
R/W EOC
6
LSB
DOUT
EOC OVR SGN MSB
DCLK
WRITE FORMAT
R/W
7
LSB
DOUT
MSB
DCLK
For Polled vs Interrupt Operation and Write Value Modified Cycle Use TC520A Data Sheet Figure 1 & 2.
Figure 1. Serial Port Timing
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
Conversion Phase Data to Serial Port Transmit Register
AZ
INT
DINT
IZ
AZ
Updated Data Ready tDR
Updated Data Ready
EOC
Figure 2. A/D Converter Timing
DETAILED DESCRIPTION Dual Slope Integrating Converter
The TC530/534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the integrator output to cross 0V (deintegrating). The resulting count is read as conversion data. A simple mathematical expression that describes dual slope conversion is: (1) Integrate Voltage = Deintegrate Voltage
(2) 1/RINTCINT
tINT VIN(t)dt = 1/RINTCINT 0
tDINT VREF 0
from which: (3) (VIN)
Another inherent benefit is noise immunity. Input noise spikes are integrated (or averaged to zero) during the integration period. The integrating converter has a noise immunity with an attenuation rate of at least -20dB per decade. Interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. For this reason, the integration period of the converter is often established to reject 50/60Hz line noise. The ability to reject such noise is shown by the plot of Figure 3. In addition to the two phases required for dual slope measurement (Integrate and Deintegrate), the TC530/534 performs two additional adjustments to minimize measurement error due to system offset voltages. The resulting four internal operations (conversion phases) performed each measurement cycle are: Auto Zero (AZ), Integrator Output Zero (IZ), Input Integrate (INT) and Reference Deintegrate (DINT). The AZ and IZ phases compensate for system offset errors and the INT and DINT phases perform the actual A/D conversion.
NORMAL MODE REJECTION (dB)
[
(tINT) (RINT)(CINT)
]
= (VREF)
[
(tDINT) (RINT)(CINT)
]
30 T = MEASUREMENT PERIOD 20
and therefore: (4) VIN = VREF
[]
tDINT tINT
10
where: VREF = Reference Voltage tINT = Integrate Time tDINT = Reference Voltage Deintegrate Time Inspection of equation (4) shows dual slope converter accuracy is unrelated to integrating resistor and capacitor values, as long as they are stable throughout the measurement cycle. This measurement technique is inherently ratiometric (i.e., the ratio between the tINT and tDINT times is equal to the ratio between VIN and VREF).
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0 0.1/T
1/T INPUT FREQUENCY
10/T
Figure 3. Integrating Converter Normal Mode Rejection
TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
Auto Zero Phase (AZ) This phase compensates for errors due to buffer, integrator and comparator offset voltages. During this phase, an internal feedback loop forces a compensating error voltage on auto zero capacitor (CAZ). The duration of the AZ phase is programmable via the serial port (see also Programming AZ and INT Phase Duration paragraph of this document). Input Integrate Phase (INT) In this phase, a current directly proportional to differential input voltage is sourced into integrating capacitor CINT. The amount of voltage stored on CINT at the end of the INT phase is directly proportional to the applied differential input voltage. Input signal polarity (sign bit) is determined at the end of this phase. Converter resolution and conversion speed is a function of the duration of the INT phase, which is programmable by the user via the serial port (see also Programming AZ and INT Phase Duration paragraph of this document). The shorter the integration time, the faster the speed of conversion, but the lower the resolution. Conversely, the longer the integration time, the greater the resolution, but at slower the speed of conversion. Reference Deintegrate Phase (DINT) This phase consists of measuring the time for the integrator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0V. The resulting timer data is stored in the output shift register as converted analog data. Integrator Output Zero Phase (IZ) This phase guarantees the integrator output is at zero volts when the AZ phase is entered so that only true system offset voltages will be compensated for. All internal converter timing is derived from the frequency source at OSCIN and OSCOUT. This frequency source must be either an externally provided clock signal, or an external crystal. If an external clock is used, it must be connected to the OSCIN pin and the OSCOUT pin must remain floating. If a crystal is used, it must be connected between OSCIN and OSCOUT and physically located as close to the OSCIN and OSCOUT pins as possible. In either case, the incoming clock frequency is divided by four and the resulting clock serves as the internal TC530/534 timebase. (1) Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, tINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection. (2) Estimate Crystal Frequency Crystal frequencies as high as 2MHz are allowed. Crystal frequency is estimated using:
FIN = 2(R) tINT
1
2 3 4 5 6 7
where: R
= Desired Converter Resolution (in counts) FIN = Input Frequency (in MHz) INT = Integration Time (in seconds)
(3) Calculate LOAD VALUE
[LOAD VALUE]10 = 256 - (tINT)(FIN) 1024
FIN can be adjusted to a standard value during this step. The resulting base -10 LOAD VALUE must be converted to a hexadecimal number, then loaded into the serial port prior to initiating A/D conversion. DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator capacitor during INT, and the value of VREF. The DINT phase is initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(max)/2). System RESET The TC530/534 must be forced into the AZ state when power is first applied. A .01F capacitor connected from RESET to VCC (or external system reset logic signal) can be used to momentarily drive RESET high for a minimum of 100msec.
Selecting Component Values for the TC530/534
(1) Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a fullscale current of 20A. The value of RINT is therefore directly calculated as follows:
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APPLICATIONS Programming the TC530/534
AZ and INT Phase Duration: These two phases have equal duration determined by the crystal (or external) frequency and the timer initialization byte (LOAD VALUE). Timing is selected as follows: TELCOM SEMICONDUCTOR, INC.
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
RINT (M) = VINMAX 20
Table 2. Recommend Capacitor for CINT
Value
0.1 0.22 0.33 0.47
Suggested Part Number*
WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .33/63/20 WIMA MK12 .47/63/20
where: VINMAX = Maximum Input Voltage (full count voltage) RINT = Integrating Resistor (in M) For loop stability, RINT should be 50k. (2) Select Reference (CREF) and Auto Zero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 1. Larger values for CAZ and CREF may also be used to limit roll-over errors. Table 1. CREF and CAZ Selection Conversions Typical Value of Suggested * Per Second CREF, CAZ (F) Part Number >7 2 to 7 2 or less 0.1 0.22 0.47 WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .47/63/20
*WIMA Corp. listing on the last page of this data sheet.
4. Calculate VREF The reference deintegration voltage is calculated using: VREF (in Volts) = (VS - 0.9)(CINT)(RINT) 2(tINT)
Serial Port Communication with the TC530/534 is accomplished over a 3 wire serial port. Data is clocked into DIN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK. R/W must be HIGH to read converted data from the serial port and LOW to write the LOAD VALUE to the TC530/ 534. Load Value Write Cycle (Figure 4) Following the power-up reset pulse, the LOAD VALUE (which sets the duration of AZ and INT) must next be transmitted to the serial port. To accomplish this, the processor monitors the state of EOC (which is available as a hardware output or at DOUT). R/W is taken low to initiate the write cycle only when EOC is low (during the AZ phase). (Failure to observe EOC low may cause an offset voltage to be developed across CINT resulting in erroneous readings). The 8 bit LOAD VALUE data on DIN is clocked in by DCLK. The processor then terminates the write cycle by taking R/W high. (Data is transferred from the serial input shift register to the time base counter on the rising edge of R/W, and data conversion is initiated). Data Read Cycle (Figure 5) Data is shifted out of the serial port in the following order: End of Conversion (EOC), Overrange (OVR), Sign (SGN), conversion data (MSB first). When R/W is high, the state of the EOC bit can be polled by simply reading the state of DOUT. This allows the processor to determine if new data is available without connecting an additional wire to the EOC output pin (this is especially useful in a polled environment). Input Multiplexer (TC534 Only) A 4 input, differential multiplexer is included in the TC534. The states of channel address lines A0 and A1 determine which differential VIN pair is routed to the con-
*WIMA Corp. listing on the last page of this data sheet.
3. Calculate Integrating Capacitor (CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e. |VDD - 0.9V| or |VSS + 0.9V|). Using the 20A buffer maximum output current, the value of the integrating capacitor is calculated using the following equation:
CINT (F) =
where: tINT VS CINT
(tINT)(20) (VS - 0.9)
= Integration Period = Applied Supply Voltage = Integrator Capacitor Value (in F)
It is critical that the integrating capacitor have a very low dielectric absorption. PPS capacitors are an example of one such chemistry. Table 2 summarizes various capacitors suitable for CINT.
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
Timing Status Power-up RESET Undefined Write LOAD VALUE to Serial Port Converter in Normal Service
1
2 3 4 5 6 7
Conversion Phase
AZ
AZ
INT
DINT
IZ
AZ...
R/W brought LOW during AZ for serial port write cycle
R/W
Continuous Conversions R/W = HIGH strobes LOAD VALUE into timebase and starts conversion
Converter held in AZ state due to RESET = 1
RESET
DCLK
DIN
1 1 MSB EOC
0
0 1 1 LOAD VALUE
1
1 LSB
Figure 4. TC530/534 Initialization and Load Value Write Cycle
verter input. A0 is the least significant address bit (i.e., channel 1 is selected when A0 = 1 and A1 = 0). The multiplexer is designed to be operated in a differential mode. For single-ended inputs, the CHx- input for the channel under selection must be connected to the ground reference associated with the input signal.
The charge pump clock operates at a typical frequency of 100kHz. If lower quiescent current is desired, the charge pump clock can be slowed by connecting an external capacitor from the OSC pin to VDD. Reference typical characteristics curves.
R/W
APPLICATIONS Design Example
Figure 6 shows a typical TC534 interrupt-driven application. Timing and component values are calculated from equations and recommendations made in the Dual Slope Integrating Converter and Programming the TC530/534 sections of this document. The EOC connection to the processor INT input is for interrupt-driven applications only. (In polled systems, the EOC output is available on DOUT). GIVEN REQUIRED RESOLUTION: 16 Bits (65,536 counts.) MAXIMUM VIN: 2V POWER SUPPLY VOLTAGE: +5V 60Hz SYSTEM 1. Pick Integration time (tINT) 66msec 2. Estimate crystal frequency FIN = 2R/tINT = 2 x 65536/66 x 10 -3 = 1.98MHz (use 2MHz)
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DCLK
DOUT
EOC
OVR POL MSB
LSB
Figure 5. Serial Port Data Read Cycle
DC/DC Converter An on-board, TC7660H-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. The charge pump develops a negative output voltage by moving charge from the power supply to the reservoir capacitor at VSS by way of the commutating capacitor connected to the CAP+ and CAP- inputs. TELCOM SEMICONDUCTOR, INC.
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5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
3. Calculate LOAD VALUE LOAD VALUE = 256 - (tINT)(FIN)/1024 = [128]10 [128]10 = 80 hex 4. Calculate RINT RINT (in M) = VINMAX/20 = 2/20 = 100k 5. Calculate CINT for maximum (4V) integrator output swing CINT (in F) = (tINT)(20 x 10 -6)/ (VS - 0.9) = (.066)(20 x 10 -6)/(4.1) = .32F (use closest value: 0.33F) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .33/63/10 6. Choose CREF and CAZ based on conversion rate Conversions/sec = 1/(tAZ + tINT + 2tINT + 2msec) = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which CAZ = CREF = 0.22F (see Table 1) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .22/63/10 7. Calculate VREF VREF (in Volts = (VS - 0.9)(CINT)(RINT) 2(tINT) = (4.1)(0.33x10 -6)(105)/2(.066) = 1.025V
Power Supply Sequencing
Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur. See Circuit Design/Layout Considerations below. Failing to insure a proper power-up sequence can cause spurious operation.
Ciruit Design/Layout Considerations
(1) Separate ground return paths should be used for the analog and digital circuitry. Use of ground planes and trace fill on analog circuit sections is highly recommended EXCEPT for in and around the integrator section and CREF, CAZ. (CINT, CREF, CAZ, RINT). Stray capacitance between these nodes and ground appears in parallel with the components themselves and can affect measurement accuracy.
+5V C1 .01F VDD .01F IN1 IN1 + - RESET VCCD VDD EOC R/W DOUT DIN DCLK TC534 CIN 0.33F CAZ 0.22F CAZ BUF RINT 100k CREF 0.22F MUX Channel Control 1F CAP - C+ REF
- CREF + VREF
+5V 10F
100
IN2 IN2 VCCD .01F 1F IN4 IN4 Analog Inputs IN3 IN3
+ -
(Optional)
INT I/O I/O I/O I/O PROCESSOR
+ -
+ -
CINT
OSCIN X1: 2MHz OSCOUT VSS DGND R2 100k -5V 1F +5V
R1 100k
A0 A1 CAP
+ - VREF
(1.03V)
TC04 (1.25V VREF)
ACOM
Figure 6. TC530/534 Typical Application 3-58
TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
(2) Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur in the internal state machines. It is recommended that the digital supply, VCCD, be powered up first. One method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. See Figure 6, TC530/534 Typical Application. (3) Decoupling capacitors, preferably a higher value electrolytic or tantulum in parallel with a small ceramic or tantalum, should be used liberally. This includes bypassing the supply connections of all active components and the voltage reference. (4) Critical components should be chosen for stability and low noise. The use of a metal-film resistor for RINT and Polypropylene or Polyphenelyne Sulfide (PPS) capacitors for CINT, CAZ, and CREF is highly recommended. (5) The inputs and integrator section are very high impedance nodes. Leakage to or from these critical nodes can contribute measurement error. A guard-ring should be used to protect the integrator section from stray leakage. (6) Circuit assemblies should be scrupulously clean to prevent the presence of contamination from assembly, handling, or the cleaning itself. Minutely conductive trace contaminates, easily ignored in most applications, can adversely affect the performance of high impedance circuits. The input and integrator sections should be made as compact and close to the TC53x as possible. (7) Digital and other dynamic signal conductors should be kept as far from the TC53x's analog section as possible. The microcontroller or other host logic should be kept quiet during a measurement cycle. Background activites such as keypad scanning, display refreshing, and power switching can introduce noise.
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TC530EV Evaluation Kit
The TC530EV consists of a 4" x 6" pre-assembled circuit board that connects to the serial port of any PC or dumb terminal. Also included is a WindowsTM* ExcelTM*-based design utility that calculates component and LOAD values based on user input, and prints a finished circuit schematic. Please contact your local TelCom representative for more information, or point your web browser to http://www.telcomsemi.com.
*All trademarks are the property of their respective owners.
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TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
TYPICAL CHARACTERISTICS
Output Voltage vs Load Current 5 4 TA = 25C V+ = 5V -0 TA = 25C -1 Output Voltage vs. Output Current
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
30 40 50 LOAD CURRENT (mA) 60 70 80
3 2 1 0 -1 -2 -3 -4 -5 0 10 20 Slope 60
-2 -3 -4 -5 -6 -7 -8 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT (mA) Output Source Resistance vs. Temperature 100
Output Ripple vs. Load Current 200
175 150 125 100 75 50 25 0 0
OUTPUT SOURCE RESISTANCE ()
OUTPUT RIPPLE (mV PK-PK)
V+ = 5V, TA = 25C Osc. Freq. = 100kHz
90 80 70 60 50 40 -50
V+ = 5V IOUT = 10mA
CAP = 1F
CAP = 10F
1
2
3
4
5
6
7
8
9
10
-25
0
25
50
75
100
LOAD CURRENT (mA) Oscillator Frequency vs. Capacitance 100 150 TA = +25C V+ = 5V
TEMPERATURE (C) Oscillator Frequency vs. Temperature V+ = 5V
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
125
10
100
75
1 1 100 OSCILLATOR CAPACITANCE (pF) 10 1000
50 -50
-25
0
25 75 50 TEMPERATURE (C)
100
125
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TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION SUBSYSTEMS TC530 TC534
WIMA Corporation Capacitor Representatives (Tables 1 and 2)
Australia: ADILAM ELECTRONICS (PTY.) LTD. P.O. Box 664 3 Nicole Close Bayswater 3153 Tel.: 3-7 61 44 66 Fax: 3-7 61 41 61 Canada: R-THETA INC. 130 Matheson Blvd. East, Unit 2 Mississauga, Ont. L4Z1Y6 Tel.: 9 05-8 90-02 21 Fax: 9 05-8 90-16 28 Hong Kong: REALTRONICS CO. LTD. E-3, Hung-On Building 2, King's Road Tel.: 25 70 11 51 Fax: 28 06 84 74 India: SUSAN AGENCIES P.O. Box 2138 Srirampuram P.O. Bangalore-560 021 Tel.: 0 80-3 32 06 62 Fax: 0 80-3 32 43 38 Israel: M.G.R. TECHNOLOGY P.O. Box 2229 Rehavot 76121 Tel.: 9 72-8-41 17 19 Fax: 9 72-8-41 41 78 Japan: UNIDUX INC. 5-1-21, Kyonan-Cho Musashino-Shi Tokyo 180 Tel.: 04 22-32-41 11 Fax: 04 22-32-03 31 Malaysia: MA ELECTRONICS (M) SDN BHD 346-B Jalan Jelutong 11600 Penang Tel.: 6 04-2 81 45 18 Fax: 6 04-2 81 45 15 Singapore: MICROTRONICS ASSOC. (PTE.) LTD. 8, Lorong Bakar Batu 03-01, Kolam Ayer Ind. Park Singapore 1334 Tel.: 65-7 48-18 35 Tlx: 34 929 Fax: 65-7 43-30 65 South Africa: KOPP ELECTRONICS LIMITED P.O. Box 3853 2128 Rivonia Tel.: 0 11-4 44-23 33 Fax: 0 11-4 44-17 06 South Korea: YONG JUN ELECTRONIC CO. #201, Sungwook Bldg. 1460-16, Seocho-Dong Seocho-Ku Seoul, Korea Tel.: 2-52 31 80 02 Fax: 2-5 23 18 03 Taiwan, R.O.C.: SOLOMON TECHNOLOGY CORP. 7th Floor No. 2 Lane 47, Sec. 3 Nan Kang Road Taipei Tel.: 8 86-2-7 88 89 89 Fax: 8 86-2-7 88 82 75 Thailand: MICROTRONICS THAI LTD. 50/68 T.T. Court Cheng Wattana Road Amphur Pak-Kreed Nonthaburi 11120 Tel.: 6 62-5 84 58 07, Ext. 102 Fax: 6 62-5 83 37 75 USA: THE INTER-TECHNICAL GROUP, INC. WIMA DIVISION 175 Clearbrook Road P.O. Box 535 Elmsford, NY 10523-0535 Tel.: 914-347-2474 Fax: 914-347-7230 TAW ELECTRONICS, INC. 4215, W. Burbank, Blvd. Burbank, CA, 91505 Tel.: 8 18-8 46-39 11 Fax: 8 18-8 46-11 94
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Venezuela: MAGNETICA, S.A. Apartado 78117 Caracas 1074 A Tel.: 58-2-2 41 75 09 Fax: 58-2-2 41 55 42
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TELCOM SEMICONDUCTOR, INC.
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